In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering signal to noise ratio and undesirable signal problems. The desired higher level of integration with reliable operation, can be achieved by making DRAM storage capacitors with the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. For example, a three-dimensional stacked capacitor is disclosed in U.S. Pat. No. 5,053,351. The storage node plate of this capacitor has an E-shaped cross-section. In another example, a stack capacitor with ladder storage node is disclosed in U.S. Pat. No. 5,451,537. The top surface of the bottom electrode is fabricated a step-like structure. These complex capacitor shapes increase the surface area of the capacitor, resulting in a higher storage capacitance. However, complex capacitor shapes tend to be complex to fabricate and may have reduced structural integrity. Accordingly, there is a need for capacitor node with high surface area that is simple to manufacture.